The present invention relates generally to clock signal generating circuits, and more particularly to a clock signal generator circuit which generates from an input clock signal having an input frequency and input duty cycle, an output clock signal having an output frequency which is a predetermined multiple of the input frequency and an output duty cycle which is a fifty percent duty cycle irrespective of the input duty cycle.
Frequency multiplying of clock signals is employed in computer systems for a number of reasons. For example, an accelerated clock signal may be necessary to adequately operate or receive asynchronous input from a storage device, such as a read only memory or ROM, which requires quick read and write speeds. Similarly, a frequency multiplier may be necessary to update data at a time other than the leading edge of an input clock signal pulse.
For instance, random access memory (RAM) cells often require precharging before and recharging after each read and write operation during a single clock cycle. In this example, a clock signal having double the frequency of the input clock signal is useful for initiating the precharge, read, recharge and write operations. In such an application, preferably the generated double frequency clock signal is characterized by rising edges simultaneous with the rising and falling edges of the input clock signal, and by falling edges simultaneous with the mid-points of each half-cycle of the input clock signal. A fifty percent duty cycle will ensure such an output signal.
According to the background art, frequency doubling with a fifty percent duty cycle output can be achieved by employing a plurality of cascaded inverters forming a tapped delay line. Such prior art design required the total amount of delay achieved by such delay lines to be predetermined according to the input frequency. The output of the delay line was connected to one input of an EXCLUSIVE OR gate. The input clock signal was applied to the input of the tapped delay line and to the second input of the EXCLUSIVE OR gate. By accurately specifying the delay generated by the cascaded inverters, the signal applied to the first EXCLUSIVE OR gate input is delayed from the input clock signal by one quarter cycle, causing the EXCLUSIVE OR gate to generate the appropriate double frequency output clock signal, as described above. The duty cycle of the double frequency signal output from the EXCLUSIVE OR gate is monitored by a control circuit using a counter device to increase or decrease the duty cycle as needed to ensure a fifty percent duty cycle for the output signal. Such a prior art apparatus is shown, for example, in U.S. Pat. No. 4,799,022 , entitled "Frequency Doubler with Duty Cycle Monitor Means," which is incorporated herein by reference.
There are numerous disadvantages inherent in such prior art. First, such prior art is not easily adapted to creating an output signal of some frequency other than double the input frequency (e.g., three or four times the input frequency). Second, the prior art requires knowledge of the input frequency before the circuit can properly function, leaving the accuracy of the output signal's frequency vulnerable to variations in the input frequency. Third, some prior art frequency multipliers are designed such that they remain unpredictably sensitive to minor variations in temperature. If a frequency multiplier is sensitive to minor variations in temperature, the duty cycle of the output signal may vary from a desired setting, such as fifty percent. This can result in erroneous operation of the "precharge, read, recharge and write" procedure discussed above.